The present invention is directed to the selective transfer of data between storage mediums.
The electronics field is becoming more competitive. New entrants to the market are generating tremendous pressure to increase efficiency of logic design, to reduce design cost, and, to reduce time to market. Extensive performance of simulation can detect design errors before a design is manufactured, and thus reduce the number of design iterations. The use of an efficient hardware description language (HDL) such as VERILOG(copyright) and a host simulation system have become invaluable for minimizing design errors, and have made it possible to fabricate functional chips in the first silicon processed.
Computers used as a host for a logic simulation program in one example employ a hierarchical information retrieval method for transferring information or data between data storage devices. One of the data storage devices is typically a mass storage device, such as a hard disk. Another of the data storage devices usually comprises a relatively faster and more accessible storage device such as random-access memory (RAM). Finally, an intermediate data storage device, such as a cache, is used to provide rapid, but usually very small, data transfers between the hard disk and random-access memory. The random-access memory is normally smaller than a hard disk and is usually a faster and more accessible storage device The relative size between the cache and the random-access memory varies. On a personal computer, the cache is usually smaller than the random access memory. On workstations and microcomputers, the cache is usually larger than the random access memory. Such a pattern commonly exists notwithstanding a use of multiple levels of hierarchy.
Common retrieval methods employ paging, swapping, or caching to improve the utilization data storage devices by reversibly transferring large blocks of information between the storage devices. While these retrieval methods normally improve the efficiency of a logic simulation program, that improved efficiency is merely a side effect rather than an intended purpose.
In prior logic simulation programs, the host simulation system uses a static memory allocation algorithm in the hardware description language which requires the employment of a random-access memory (hereinafter referred to as a xe2x80x9cmemory arrayxe2x80x9d) of a size at least equal to the entire simulated memory size. Thus, the permitted size of information or data transfers is determined largely by the physical size of the memory array. If, for example, a 128 megabit hard memory device is called for by the logic simulation program and the memory array has enough capacity, the entire contents of the hard memory device is transferred into the memory array. This can create substantial inefficiencies, especially with hard memory devices that are large.
Prior logic simulation programs are limited to either using expensive, large memory 15 arrays or performing the time-consuming operation of transferring the contents of relatively small increments of memory to the memory array, regardless of the usefulness of a particular memory increment. A need exists for a logic simulation program that does not use a full memory transfer like that utilized by the static memory allocation algorithm. Accordingly, the present invention provides a dynamic memory allocation algorithm for the hardware description language, that adjusts the amount of data transferred to the memory array, and, for example, can transfer less than the entire contents of a hard memory device in a logic simulation program. Fewer data transfers are made to the memory array. Thus, the total size of the data transferred to the memory array, in a logic simulation program employing the present invention, is much smaller than the entire size of the memory that is simulated.
A hardware description language (HDL) such as VERILOg(copyright) does not have a dynamic memory allocation scheme in its native format. This forces designers to use a static memory allocation scheme when they use the standard IDL. Through. employment of the present invention, a logic simulation program, in which circuit information is described with an HDL such as VERIILOG, can use the circuit information both as input to a circuit simulation and as addressing information. The addressing information is then used to provide hierarchical information retrieval within the simulation data, thereby reducing the amount of data that is to be transferred between a storage device, such as a cache (hereinafter referred to as a xe2x80x9cdump memoryxe2x80x9d), and a storage device, such as a memory array. Since the amount of data that needs to be transferred is reduced, the time required for transferring this data is consequently reduced, thereby increasing the efficiency of the logic simulation program utilizing the storage devices. The use of the addressing information also reduces the size required of a dump memory and a memory array for a certain performance.
The present invention also uses the circuit information for partitioning structures, such as in hard memory devices, into more convenient sizes for simulation, for instance, by a logic simulation program. The addressing information may also be used for generating tables of information about the structure of the objects, such as in hard memory, which are to be partitioned or paged into a memory array. This further enhances the speed of and reduces the size of information transfers.
The present invention in one example provides a system for selectively transferring data between storage devices in a computer system. The system includes a first data storage device, a second data storage device, a third data storage device, and a computer readable signal bearing medium. Means in the medium transfers application data and non-application data from the first data storage device to the second data storage device. Means in the medium examines data in the second data storage device to identify the application data. Means in the medium derives a secondary address for the application data. Means in the medium transfers only application data indicated by the secondary address from the second data storage device to the third data storage device. Means in the medium parses the application data indicated by the secondary address. Means in the medium transfers parsed application data from the third data storage device to the second data storage device. Means in the medium transfers the parsed application data and the non-application data from the second data storage device to the first data storage device. Means in the medium dumps unexamined data to the second data storage device.
The present invention in another example comprises a system for selectively transferring data between storage devices in a computer system. The system includes a first data storage device that stores the application data and non-application data. A second data storage device receives a dump of at least a part of the application data and the non-application data from the first data storage device. A memory controller examines data in the second data storage device to identify the application data and derive a secondary address for the application data. A third data storage device receives only application data indicated by the secondary address from the second data storage device. The memory controller parses the application data indicated by the secondary address; transfers parsed application data from the third data storage device to the second data storage device, transfers the parsed application data and the non-application data from the second data storage device to the first data storage device, and dumps unexamined data from the first data storage device to the second data storage device.
It is an object of the present invention to provide an improved logic simulation program which requires less time, and uses less expensive hardware, to perform a logic simulation.
Another object of the present invention is to perform a logic simulation with an algorithm that dynamically changes the size of data transferred to the memory array, so that the total size of the data transferred is much smaller than the entire size of the memory that is simulated.
A further object of the present invention is to perform a logic simulation with an algorithm that transfers less data than would occupy the entire simulated memory to a memory array.
Other and further advantages, embodiments, variations and the like will be apparent to those of skill in the art from the present specification taken with the accompanying drawings and appended claims.